OPERATING SYSTEMS / 1. HARDWARE — CPU, RAM, STORAGE
Hardware — CPU, RAM, Storage & Motherboard
The physical foundation: what each component is and how they connect
EXPLANATION
Understanding hardware means understanding what physically exists in your machine. Every computation, every byte of memory, every file — all of it is ultimately electrons flowing through physical matter. The Motherboard — the backbone: The motherboard is the main circuit board that connects everything. It contains: • CPU socket — where the processor sits • RAM slots (DIMM) — where memory sticks plug in • PCIe slots — for GPU, NIC, SSDs (NVMe) • Chipset — mediates communication between CPU and peripherals • BIOS/UEFI chip — non-volatile ROM that holds firmware • Power connectors — from the PSU (Power Supply Unit) • SATA ports — for HDDs and SSDs • USB, audio, display headers CPU (Central Processing Unit) — the brain: The CPU executes instructions. Modern CPUs contain: • Cores — independent processing units. 4-core = 4 instructions simultaneously • Threads (Hyper-Threading/SMT) — each core can run 2 threads by sharing execution units • Cache hierarchy: - L1 cache: 32-64 KB per core. ~4 cycles latency. Holds the hottest data - L2 cache: 256 KB – 1 MB per core. ~12 cycles latency - L3 cache: 8–32 MB shared. ~40 cycles latency - Main RAM: 16+ GB. ~100-300 cycles latency - NVMe SSD: microseconds. SSD: milliseconds • ALU (Arithmetic Logic Unit) — does math and logic • Control Unit — decodes instructions, coordinates execution • Registers — tiny storage inside CPU (RAX, RBX, RSP, RIP…). Nanosecond access The Fetch-Decode-Execute cycle (the CPU's heartbeat): ① Fetch: read the instruction at memory address stored in IP/PC register ② Decode: figure out what the instruction means (ADD, LOAD, JUMP…) ③ Execute: perform the operation (ALU computes, memory is read/written) ④ Update IP/PC: move to next instruction (unless it was a JUMP) Repeat ~3 billion times per second (3 GHz clock) RAM (Random Access Memory) — working memory: • Volatile — data is lost when power is off • DRAM (Dynamic RAM) — capacitors leak and must be refreshed thousands of times per second • DDR4/DDR5 — Double Data Rate, transfers data on both rising and falling clock edges • RAM is byte-addressable: every byte has a unique address (0 to RAM_SIZE-1) • When you open a program, it's loaded from disk into RAM. CPU reads/writes RAM Storage: • HDD (Hard Disk Drive) — rotating magnetic platters. Slow (seek time ~5ms), cheap, large. 100 MB/s • SSD (Solid State Drive) — NAND flash chips. No moving parts. ~500 MB/s (SATA) or 3-7 GB/s (NVMe) • NVMe — SSD directly on PCIe bus. Bypasses SATA controller. Much faster • Data persists without power (non-volatile) Memory Hierarchy principle: faster storage = smaller and more expensive. The OS and hardware work together to keep frequently used data in the fastest possible storage.
DIAGRAM
MOTHERBOARD LAYOUT:
┌─────────────────────────────────────────────────────┐
│ [CPU Socket] [RAM Slot 1] [RAM Slot 2] │
│ [RAM Slot 3] [RAM Slot 4] │
│ [PCIe x16 ───→ GPU] │
│ [PCIe x4 ───→ NVMe SSD] │
│ [PCIe x1 ───→ NIC] │
│ [BIOS Chip] [Chipset] [SATA ports] │
│ [USB Headers] [Audio] [Power connectors] │
└─────────────────────────────────────────────────────┘
CPU INTERNALS:
┌─────────────────────────────────────┐
│ Core 0 Core 1 │
│ ┌───────────┐ ┌───────────┐ │
│ │L1-I L1-D │ │L1-I L1-D │ │
│ │ L2 cache │ │ L2 cache │ │
│ └───────────┘ └───────────┘ │
│ └──────┬──────┘ │
│ L3 Cache (shared) │
│ │ │
│ Memory Controller │
└─────────────┼───────────────────── ┘
│
DDR4/5 RAM
MEMORY LATENCY (CPU cycles):
Registers: 1 cycle (~0.3 ns)
L1 cache: 4 cycles (~1 ns)
L2 cache: 12 cycles (~4 ns)
L3 cache: 40 cycles (~12 ns)
RAM: 200 cycles (~60 ns)
NVMe SSD: ~100,000 cycles (~30 µs)
HDD: ~10,000,000 cycles (~3 ms)CODE