COMPUTER ORGANIZATION & ARCHITECTURE / 6. CPU DATAPATH & CONTROL
CPU Datapath & Control Unit
How instructions flow through the CPU — fetch, decode, execute
EXPLANATION
The CPU has two major subsystems that work together: the Datapath (the hardware that moves and processes data) and the Control Unit (the logic that tells the datapath what to do for each instruction). The Datapath contains: - Program Counter (PC) — holds address of next instruction - Instruction Memory — stores the program (read-only during execution) - Register File — 16–32 general purpose registers - ALU — does all computation - Data Memory (RAM) — stores data the program reads/writes - Sign extender — extends immediate values to full width - MUXes — select between different data sources The Control Unit: - Takes the instruction opcode as input - Produces control signals that configure the datapath MUXes and units - Decides: does the ALU add or subtract? Does the result go to a register or memory? Is the next PC = PC+4 or a branch target? - Implemented as a truth table (combinational) or state machine (for complex ISAs) The Fetch-Decode-Execute cycle in detail: FETCH: ① Read instruction from Instruction Memory at address PC ② Instruction register holds the fetched instruction ③ PC = PC + 4 (increment for next instruction) DECODE: ④ Split instruction into fields: opcode, source registers, destination register, immediate ⑤ Control unit reads opcode → sets all control signals ⑥ Register file reads source registers (happens in parallel with control decode) EXECUTE: ⑦ ALU performs operation on register values (or register + immediate) ⑧ If load/store: compute memory address (register + offset) ⑨ If branch: compute branch target address, evaluate condition flags MEMORY: ⑩ If load: read data memory at computed address ⑪ If store: write register value to data memory WRITE-BACK: ⑫ Write result back to destination register in register file Single-cycle vs Multi-cycle: - Single-cycle: one instruction per clock cycle. Clock must be slow enough for slowest instruction (memory access limits this) - Multi-cycle: different instructions take different number of cycles. Clock can be faster (tuned to one stage). But requires state between cycles → more hardware RISC vs CISC: - RISC (ARM, RISC-V): simple fixed-length instructions, load-store architecture (only LOAD/STORE access memory, all computation on registers), many registers. Easier to pipeline. - CISC (x86): complex variable-length instructions, memory operands in arithmetic, many addressing modes. x86 CPUs internally translate CISC instructions to RISC-like micro-ops before execution.
DIAGRAM
SINGLE-CYCLE DATAPATH (simplified RISC):
┌─────┐ addr ┌──────────┐ instr
│ PC │───────→│ Instr │──────────────────────────────┐
└──┬──┘ │ Memory │ │
│ └──────────┘ ↓
│ PC+4 ┌─────────────────┐
└──────────────────────────────────────→MUX │ Control Unit │
↑ │ (opcode → ctrl)│
Branch └────────┬────────┘
target │ control signals
↓
instr[rs1] ──→ ┌───────────┐ ┌─────┐ ┌──────────────┐
instr[rs2] ──→ │ Register │→ A ────→│ │ │ │
instr[rd] ──→ │ File │→ B ─┬──→│ ALU │───→│ Data Memory │
write data ──→ │ │ │ │ │ │ (RAM) │
└───────────┘ │ └─────┘ └──────────────┘
│ ↑ ALU_op │ read data
imm ──┴─MUX ↓
┌───────┐
│ MUX │→ write back
└───────┘ to reg file
CONTROL SIGNALS (example for ADD R1, R2, R3):
RegDst=1 (dest = rd field)
ALUSrc=0 (ALU B input = register, not immediate)
MemtoReg=0 (write ALU result, not memory, to register)
RegWrite=1 (write to register file)
MemRead=0 (don't read memory)
MemWrite=0 (don't write memory)
Branch=0 (not a branch)
ALUop=ADDCODE