COMPUTER ORGANIZATION & ARCHITECTURE / 9. ISA — X86-64 & ARM
Instruction Set Architecture — x86-64 & ARM
The contract between hardware and software — what the programmer sees
EXPLANATION
The Instruction Set Architecture (ISA) is the abstract model of a computer that software is written for. It defines everything a programmer (or compiler) needs to know: what instructions exist, what registers are available, how memory is addressed, and what the calling convention is. The ISA is a contract: Intel can redesign the transistors, change the pipeline, add new microarchitecture features — as long as the ISA behavior is preserved, all existing software continues to work. This is why a program compiled for x86 in 1990 still runs on your 2024 Intel CPU. x86-64 (AMD64) — the dominant desktop/server ISA: - CISC (Complex Instruction Set Computer) - Variable-length instructions: 1 to 15 bytes per instruction - 16 general-purpose 64-bit registers: RAX, RBX, RCX, RDX, RSI, RDI, RSP, RBP, R8-R15 - Special registers: RIP (instruction pointer), RFLAGS (status flags) - Memory operands: instructions can directly operate on memory (not just registers) - Internally: CPU translates CISC instructions into RISC-like micro-ops before execution Key x86-64 registers and their conventional uses: - RAX — accumulator, return value from functions - RBX — base register (callee-saved) - RCX — counter (loop variable) - RDX — data (second argument, used in multiply/divide) - RSI/RDI — source/destination index (string ops), first two function arguments - RSP — stack pointer (top of stack) - RBP — base pointer (stack frame base) - R8-R15 — additional general purpose - XMM0-XMM15 — 128-bit SIMD registers (SSE/AVX) ARM (AArch64) — the dominant mobile/embedded ISA, now servers and Macs: - RISC (Reduced Instruction Set Computer) - Fixed-length instructions: always 4 bytes (32-bit) - 31 general-purpose 64-bit registers: X0-X30 (W0-W30 for 32-bit view) - X0-X7: function arguments and return values - X29: frame pointer, X30: link register (return address), SP: stack pointer - Load-Store architecture: ONLY LOAD and STORE can access memory. All arithmetic is register-to-register. - Condition codes on every instruction (ARM can conditionally execute most instructions) - Much simpler to pipeline than x86 — one reason Apple Silicon is so fast Calling Conventions (ABI — Application Binary Interface): How functions pass arguments and return values: - x86-64 System V (Linux/Mac): RDI, RSI, RDX, RCX, R8, R9 for first 6 args; stack for more; RAX for return - x86-64 Windows: RCX, RDX, R8, R9 for first 4 args; stack for more - ARM64: X0-X7 for first 8 args; X0 for return Stack conventions: RSP/SP must be 16-byte aligned before a CALL instruction. CALL pushes return address. RET pops and jumps to it. RISC-V — the open source ISA gaining momentum: - Royalty-free, open standard - Base instruction set (RV32I/RV64I): only ~47 instructions - Modular extensions: M (multiply), A (atomic), F (float), D (double), C (compressed 16-bit) - Growing in embedded, academia, and now data center chips
DIAGRAM
x86-64 REGISTER FILE:
63 31 15 8 7 0
│──RAX────│──EAX──│AH│AL│ General purpose
│──RBX────│──EBX──│BH│BL│ (backward compat:
│──RCX────│──ECX──│CH│CL│ can access 8/16/32/64
│──RDX────│──EDX──│DH│DL│ bit views)
│──RSI────│──ESI──│──SI──│
│──RDI────│──EDI──│──DI──│
│──RSP────│──ESP──│──SP──│ Stack pointer
│──RBP────│──EBP──│──BP──│ Frame pointer
│──R8─────│──R8D──│─R8W──│
... ...
│──R15────│──R15D─│─R15W─│
│──RIP────│ ← Instruction Pointer
FUNCTION CALL (x86-64 System V):
C code: long add(long a, long b) { return a + b; }
Assembly: mov rax, rdi ; return value = first arg
add rax, rsi ; add second arg
ret ; return (pops RIP from stack)
Caller: mov rdi, 5 ; first arg = 5
mov rsi, 3 ; second arg = 3
call add ; push RIP, jump to add
; result now in RAX = 8
ARM vs x86 (same operation):
x86: add rax, [rbx + 8] ← memory operand directly in ALU op
ARM: ldr x1, [x0, #8] ← LOAD first
add x0, x0, x1 ← then ALU op on registers onlyCODE