COMPUTER ORGANIZATION & ARCHITECTURE / 4. SEQUENTIAL CIRCUITS
Sequential Circuits — Flip-Flops & Registers
Adding memory to circuits — state that persists across clock cycles
EXPLANATION
Sequential circuits have MEMORY — their output depends on both current inputs AND past history (stored state). This is what makes computers able to remember and compute over time. The Clock: All sequential circuits are driven by a clock signal — a square wave that alternates between 0 and 1 at a fixed frequency (e.g. 3 GHz = 3 billion cycles per second). State only changes on clock edges (rising edge: 0→1, or falling edge: 1→0). This synchronization is what makes complex digital systems work reliably. SR Latch — the simplest memory element: - Built from 2 cross-coupled NAND (or NOR) gates - S (Set) input → forces output Q=1 - R (Reset) input → forces output Q=0 - Neither active → holds previous state (MEMORY!) - Both active → FORBIDDEN state (both outputs try to be same value — race condition) - Latch is level-triggered: responds to input levels, not edges D Flip-Flop — the workhorse of digital design: - D (Data) input + Clock - On rising clock edge: Q captures whatever D is at that moment - Holds that value until the next rising edge - Eliminates the forbidden state problem of SR latch - Built from: SR latch + gating logic This is the key insight: the D flip-flop is a 1-bit memory cell. It stores ONE bit. It updates only on clock edges. The entire CPU state (all registers) is made of D flip-flops. Register — N D flip-flops sharing a clock: - 8 D flip-flops → 8-bit register (stores one byte) - 64 D flip-flops → 64-bit register (x86-64 general purpose register: RAX, RBX...) - Your CPU has 16 general purpose 64-bit registers = 16 × 64 = 1024 flip-flops just for registers Register File: - A bank of registers with read/write ports - 2 read ports (can read 2 registers simultaneously for ALU inputs) - 1 write port (write ALU result back) - Controlled by register addresses from the instruction decoder Counter — register that increments each clock cycle: - Program Counter (PC/IP) is a counter: holds address of next instruction - Increments by instruction size after each fetch - Can be loaded with new value for jumps and branches Shift Register — bits shift left or right each clock: - Used for serial-to-parallel conversion - Used in multiplication (shift left = multiply by 2) - Used in CRC computation (checksums, error detection)
DIAGRAM
SR LATCH (NOR-based):
S ──→ NOR ──→──┐ Q
↑ ├──→ NOR
R ──→ NOR ──→──┘ Q'
(cross-coupled: each output feeds back to other's input)
State table:
S R | Q(next)
────┼─────────
0 0 | Q(prev) ← HOLD (memory!)
0 1 | 0 ← RESET
1 0 | 1 ← SET
1 1 | ??? ← FORBIDDEN
D FLIP-FLOP (edge-triggered):
D ──→[D FF]──→ Q
CLK──→[ ]
On ↑ of CLK: Q ← D
REGISTER (4-bit, parallel load):
D3 D2 D1 D0 ← data inputs
│ │ │ │
[FF][FF][FF][FF] ← 4 D flip-flops
│ │ │ │
Q3 Q2 Q1 Q0 ← stored value
All share same CLK → update together
CPU REGISTER FILE:
Read addr 1 ─→ ┌──────────────┐ ─→ Data out 1 (to ALU)
Read addr 2 ─→ │ Register │ ─→ Data out 2 (to ALU)
Write addr ─→ │ File │
Write data ─→ │ (16 × 64b) │
Write enable─→ └──────────────┘CODE