Transistors & Logic Gates

Everything your computer does — every calculation, every pixel, every bit of memory — is ultimately the result of transistors switching on and off billions of times per second.

The Transistor — a voltage-controlled switch:
A transistor (specifically MOSFET — Metal Oxide Semiconductor Field Effect Transistor) has three terminals:
- Gate — the control input. Apply voltage → transistor turns ON (conducts)
- Source — where current flows from
- Drain — where current flows to

NMOS (N-type): Gate HIGH → switch ON (conducts). Gate LOW → switch OFF.
PMOS (P-type): Gate LOW → switch ON. Gate HIGH → switch OFF.
CMOS (Complementary MOS): uses both NMOS and PMOS together. This is what ALL modern chips use. Extremely low power — only draws current during switching, not when idle.

Process node (nm): the "7nm", "3nm" numbers refer to the approximate size of transistor features. Smaller = more transistors per mm² = more power + less energy. Apple M3 at 3nm has ~300 million transistors per mm².

From transistors to logic gates:
A logic gate implements a Boolean function using transistors. The key insight: you never need to design with transistors directly — gates are the abstraction layer.

NAND gate (2 NMOS + 2 PMOS transistors):
- Output is LOW only when BOTH inputs are HIGH
- NAND is a UNIVERSAL GATE — you can build ANY circuit using only NAND gates
- NOR is also universal

The 7 fundamental gates: NOT, AND, OR, NAND, NOR, XOR, XNOR

NOT (inverter): simplest gate, 1 PMOS + 1 NMOS. Output = opposite of input.
AND: NOT(NAND). Output HIGH only when all inputs HIGH.
OR: NOT(NOR). Output HIGH when any input HIGH.
XOR: Output HIGH when inputs DIFFER. Critical for arithmetic (used in adders).
XNOR: Output HIGH when inputs are SAME. Used in comparators.

Why NAND is preferred in real chips: NAND gates are faster and smaller than AND gates (AND = NAND + NOT = 6 transistors vs NAND's 4). Chip designers build everything from NAND/NOR.

Propagation delay: gates aren't instantaneous. Each gate introduces a small delay (~10-100 picoseconds). The longest path of gates from input to output is the critical path — it determines the maximum clock speed.

1# Simulate all logic gates in Python
2# This IS what silicon does — we're just doing it in software
3
4def NOT(a): return int(not a)
5def AND(a, b): return a & b
6def OR(a, b):  return a | b
7def NAND(a, b): return NOT(AND(a, b))
8def NOR(a, b):  return NOT(OR(a, b))
9def XOR(a, b):  return (a | b) & NOT(AND(a, b))
10def XNOR(a, b): return NOT(XOR(a, b))
11
12# Print truth table for any gate
13def truth_table(name, gate, inputs=2):
14    print(f"
15{name} Truth Table:")
16    if inputs == 1:
17        print("  A | Out")
18        print("  ──┼────")
19        for a in range(2):
20            print(f"  {a} |  {gate(a)}")
21    else:
22        print("  A  B | Out")
23        print("  ────┼────")
24        for a in range(2):
25            for b in range(2):
26                print(f"  {a}  {b} |  {gate(a, b)}")
27
28truth_table("NOT",  NOT,  inputs=1)
29truth_table("AND",  AND)
30truth_table("OR",   OR)
31truth_table("NAND", NAND)
32truth_table("XOR",  XOR)
33
34# ── Build AND from NAND (universal gate demo) ──────────
35def AND_from_NAND(a, b):
36    nand_out = NAND(a, b)
37    return NAND(nand_out, nand_out)  # NAND with itself = NOT = AND!
38
39print("
40AND built from NAND gates only:")
41for a in range(2):
42    for b in range(2):
43        result = AND_from_NAND(a, b)
44        verify = AND(a, b)
45        print(f"  AND({a},{b}) = {result}  ✓" if result == verify else "  WRONG!")
46
47# ── Propagation delay simulation ───────────────────────
48import time
49
50GATE_DELAY_NS = 0.05  # 50 picoseconds per gate (real chips)
51
52def delayed_gate(name, gate, *args):
53    result = gate(*args)
54    # time.sleep(GATE_DELAY_NS * 1e-9)  # too small to measure
55    return result
56
57print("
58Gate delays (theoretical for a 5-gate critical path):")
59print(f"  5 gates × {GATE_DELAY_NS*1000:.0f}ps = {5*GATE_DELAY_NS*1000:.0f}ps = {5*GATE_DELAY_NS:.2f}ns")
60print(f"  Max clock freq ≈ {1/(5*GATE_DELAY_NS*1e-9)/1e9:.1f} GHz")